The continuing objective of increasing the integration density of semiconductor architectures has brought about the need for extremely fine (sub-micron) resolution patterning methodologies through which a semiconductor topology is defined. Because of the presence of anomalies during the patterning process employing conventional mask configurations, current photolithographic techniques are able to achieve line widths on the order of 0.8 um.
More particularly, FIGS. 1(A)-(C) diagrammatically illustrate the photolithographic patterning of a single resist masking layer 104 atop a semiconductor substrate 101, using an overlying photomask 110 having an aperture 112 through which the photoresist layer 104 is exposed to a source of ultraviolet light 114. After development a corresponding aperture 116 extends through layer 104 so as to expose a selected portion of the surface of the substrate. Although diagrammatically illustrated in FIGS. 1(A)-(C) as having a generally planar surface, in reality it can be expected that the top surface of substrate 101 will contain an undulating or `stepped` surface, as shown at 120 in FIGS. 1(D)-(F). When such a step is located within the confines of a photomask window, as diagrammatically shown in FIG. 1(E), it may introduce an inaccuracy in the dimensions of the exposed region, as illustrated in FIG. 1(F).
Where the etching mask comprises a multilayer configuration, such as the conventional bilevel and trilevel structures of FIGS. 2(A)-2(D) and FIGS. 3(A)-3(D), respectively, additional processing problems are present. For example, in a bilevel structure, photoresist layer 104 becomes an `upper` resist layer that is formed on a `lower` photoresist layer 102, atop an underlying substrate. During the formation of such a mask, it is not uncommon for there to be an intermixing of or chemical reaction between the two photoresist layers, which causes an unwanted residue layer to remain after development of the lower photoresist layer. (The upper photoresist layer 104 is first exposed and developed to form an aperture 112 through which lower photoresist layer 102 is exposed and thereafter developed to expose a selected portion of the surface of substrate 101.)
To circumvent this intermixing problem, the bilevel mask configuration may be augmented by the provision of an intermediate oxide layer 103, thus forming a trilevel structure. Specifically, as illustrated in FIGS. 3(A)-3(D) an intermediate oxide layer 103 may be vapor-deposited between the lower photoresist layer 102 and upper photoresist layer 104. In the course of selectively exposing the surface of the underlying substrate, the aperture 112 through upper resist layer 104 is used to etch the exposed oxide layer 103, after which lower resist layer 102 is exposed (through the patterned oxide layer 103) and developed to complete the trilevel mask fabrication process. Because upper photoresist layer 104 is not formed directly on lower resist layer 102, intermixing of these two resist layers is prevented. However, the use of the additional intermediate oxide layer adds complexity to the bilevel process, without effectively improving upon line width resolution.